Enhanced channel strain to reduce contact resistance in nmos fet devices

ABSTRACT

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation Application of U.S. application Ser.No. 17/170,601, filed Feb. 8, 2021, now U.S. Pat. No. 11,574,907, whichis a Continuation Application of U.S. application Ser. No. 16/725,553,filed Dec. 23, 2019, now U.S. Pat. No. 10,916,546, which is aContinuation Application of U.S. application Ser. No. 16/105,925, filedAug. 20, 2018, now U.S. Pat. No. 10,515,966, which is a ContinuationApplication of U.S. patent application Ser. No. 15/446,295, filed Mar.1, 2017, now U.S. Pat. No. 10,056,383, which is a Divisional Applicationof U.S. application Ser. No. 14/859,165, filed Sep. 18, 2015, now U.S.Pat. No. 9,607, 838, the subject matter of each of which is incorporatedherein by reference in their entireties.

TECHNICAL FIELD

The disclosure relates to a semiconductor integrated circuit, moreparticularly to a semiconductor device having fin field effecttransistor (Fin FET) structures and its manufacturing process.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower costs, challenges from both fabrication and design issues haveresulted in the development of three-dimensional designs, such as a FinFET. Fin FET devices are a type of multi-gate structure that typicallyinclude semiconductor fins with high aspect ratios and in which channeland source/drain regions of semiconductor transistor devices are formed.A gate is formed over and along the sides of the fin structure (e.g.,wrapping) utilizing the advantage of the increased surface area of thechannel and source/drain regions to produce faster, more reliable andbetter-controlled semiconductor transistor devices. In some devices,strained materials in the source/drain regions of the Fin FET deviceutilize, for example, phosphorous doped silicon-containing epitaxiallayering.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It is tobe understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of thepresent disclosure. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. It is notedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale. In fact, the dimensions of the variousfeatures may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is an exemplary perspective view of a Fin Field-Effect Transistor(Fin FET) device in accordance with some embodiments of the presentdisclosure.

FIG. 2 is an exemplary cross sectional view of the Fin FET device havingfin structures along a gate electrode in accordance with someembodiments of the present disclosure.

FIGS. 3-19 illustrate examples of cross-sectional views of intermediatestages in the sequential fabrication process of a Fin FET structure inaccordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“made of” may mean either “comprising” or “consisting of.”

FIG. 1 is an exemplary perspective view of a Fin Field-Effect Transistor(Fin FET) device 100 having a fin structure according to one embodimentof the present disclosure, and FIG. 2 is an exemplary cross sectionalview of the Fin FET device 100 having a fin structure along a gateelectrode according to one embodiment of the present disclosure. Inthese figures, some layers/features are omitted for simplification.

The Fin FET device 100 depicted in FIGS. 1 and 2 includes, among otherfeatures, a substrate 110, a fin structure 120, a gate dielectric layer130 and a gate electrode 140. In this embodiment, the substrate 110 is asilicon substrate. Alternatively, the substrate 110 may comprise anotherelementary semiconductor, such as germanium; a compound semiconductorincluding IV-IV compound semiconductors such as SiC and SiGe, III-Vcompound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP,AlGaN, AllnAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinationsthereof. In one embodiment, the substrate 110 is a silicon layer of anSOI (silicon-on insulator) substrate. When an SOI substrate is used, thefin structure 120 may protrude from the silicon layer of the SOIsubstrate or may protrude from the insulator layer of the SOI substrate.In the latter case, the silicon layer of the SOI substrate is used toform the fin structure 120. Amorphous substrates, such as amorphous Sior amorphous SiC, or insulating material, such as silicon oxide may alsobe used as the substrate 110. The substrate 110 may include variousregions that have been suitably doped with impurities (e.g., p-type orn-type conductivity).

The fin structure 120 is disposed over the substrate 110. The finstructure 120 may be made of the same material as the substrate 110 andmay continuously extend from the substrate 110. In this embodiment, thefin structure 120 is made of silicon (Si). The silicon layer of the finstructure 120 may be intrinsic, or appropriately doped with an n-typeimpurity or a p-type impurity.

In FIG. 1 , one fin structure 120 is disposed over the substrate 110,while in FIG. 2 , three fin structures 120 are disposed over thesubstrate 110. However, the number of the fin structures is not limitedto one or three. The numbers may be two or four or more. In addition,one or more dummy fin structures may be disposed in contact with bothsides of the fin structures 120 to improve pattern fidelity inpatterning processes. The width W of the fin structure 120 is in a rangefrom about 5 nm to about 40 nm in some embodiments, and is in a rangefrom about 7 nm to about 12 nm in certain embodiments. The height H ofthe fin structure 120 is in a range from about 100 nm to about 100 nm insome embodiments, and is in a range from about 50 nm to about 100 nm inother embodiments.

In FIG. 2 , spaces between the fin structures 120 and/or a space betweenone fin structure and another element formed over the substrate 110 arefilled by an isolation insulating layer (e.g., isolation region 150)including one or more layers of insulating materials. The insulatingmaterials for the isolation region 150 may include one or more layers ofsilicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN,fluoride-doped silicate glass (FSG), or a low-K dielectric material.

The lower part of the fin structure 120 under the gate electrode 140 isreferred to as a well region 120A, and the upper part of the finstructure 120 is referred to as a channel region 120B, as shown in FIG.2 . Under the gate electrode 140, the well region 120A is embedded inthe isolation region 150, and the channel region 120B protrudes from theisolation region 150. A lower part of the channel region 120B may alsobe embedded in the isolation region 150 to a depth of about 1 nm toabout 5 nm.

The channel region 120B protruding from the isolation region 150 iscovered by a gate dielectric layer 130, and the gate dielectric layer130 is further covered by a gate electrode 140. Part of the channelregion 120B not covered by the gate electrode 140 functions as a sourceand/or drain of the Fin FET device 100 (see, FIG. 1 ).

In certain embodiments, the gate dielectric layer 130 includes a singlelayer or alternatively a multi-layer structure, having one or moredielectric materials, such as a single layer of silicon oxide, siliconnitride, or high-k dielectric material, other suitable dielectricmaterial, and/or combinations thereof, or a multilayer of two or more ofthese materials. Examples of high-k dielectric material include HfO₂,HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, zirconium oxide, aluminum oxide,titanium oxide, hafnium dioxide-alumina (HfO₂-Al₂O₃) alloy, othersuitable high-k dielectric materials, and/or combinations thereof.

The gate electrode 140 includes one or more layers of any suitablematerial, such as polysilicon, aluminum, copper, titanium, tantalum,tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobaltsilicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, othersuitable materials, and/or combinations thereof. The gate structure maybe formed using a gate-last or replacement gate methodology.

In certain embodiments of the present disclosure, one or more workfunction adjustment layers 160 is interposed between the gate dielectriclayer 130 and the gate electrode 140. The work function adjustment layer160 may include a single layer or alternatively a multi-layer structure,such as various combinations of a metal layer with a selected workfunction to enhance the device performance (work function metal layer),liner layer, wetting layer, adhesion layer, metal alloy or metalsilicide. The work function adjustment layers 160 are made of one ormore conductive materials such as a single layer of Ti, Ag, Al, TiAlN,TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co,Ni, other suitable metal materials, or a multilayer of two or more ofthese materials. In some embodiments, the work function adjustment layer160 may include a first metal material for the n-channel Fin FET and asecond metal material for the p-channel Fin FET. For example, the firstmetal material for the n-channel Fin FET may include metals having awork function substantially aligned with a work function of thesubstrate conduction band, or at least substantially aligned with a workfunction of the conduction band of the channel region 120B. Similarly,for example, the second metal material for the p-channel Fin FET mayinclude metals having a work function substantially aligned with a workfunction of the substrate valence band, or at least substantiallyaligned with a work function of the valence band of the channel region120B. In some embodiments, the work function adjustment layer 160 mayalternatively include a polysilicon layer. The work function adjustmentlayer 160 may be formed by ALD, PVD, CVD, e-beam evaporation, or othersuitable process. Further, the work function adjustment layer 160 may beformed separately for the n-channel Fin FET and the p-channel Fin FETwhich may use different metal layers.

Source and drain regions 125 are also formed in the upper part of thefin structure 120 not covered by the gate electrode 140, byappropriately doping impurities in the source and drain regions 125. Analloy of Si or Ge and a metal such as Co, Ni, W, Ti or Ta may be formedon the source and drain regions 125. In some aspects, strained materialsin the source and drain regions 125 utilize, for example, phosphorousdoped silicon-containing epitaxial layering.

An ion implantation is generally implemented for forming the source anddrain regions 125. For example, an N-type source/drain process includesa room-temperature phosphorus ion implantation that is provided to formthe phosphorus doped silicon-containing epitaxial layering. In NMOS FinFET structures (e.g., n-type source/drain regions), channel mobility isadversely impacted by parasitic capacitance that is formed after the ionimplantation. In one approach to reduce the parasitic capacitance, thephosphorus ion implantation is performed with a relatively highconcentration of single-atom phosphorus (e.g., above 1×10²¹ atoms/cm³).Although the higher concentration can yield higher doping, since somephosphorus atoms can cluster locally (e.g., form Si₃P₄ compound) and actas stressors, the ion implantation induces lower dopant activation. Toovercome the lower activation, another approach includes a hightemperature anneal to activate the dopants and possibly cure damageresulting from the ion implantation. However, the increase intemperature for the thermal anneal causes an undesirable strain loss inthe channel region 120B.

The present disclosure provides for the reduction of contact capacitanceand increase in channel mobility for NMOS Fin FET structures byproviding relatively heavy and shallow doping on a top surface of thephosphorus doped silicon-containing epitaxial layer. In particular, aphosphorus dimer (P₂ ⁺) ion implantation is utilized after the epitaxialgrowth operation in order to effectively incorporate a higher chemicalphosphorus concentration and to cause a higher amorphous level than theconventional phosphorus ion implantation under a same implantationenergy. The phosphorus dimer ion implantation may be, or may be a partof, a cryo-implantation with temperatures below about −20° C. to inducea higher amorphous level (or lower activation energy).

FIGS. 3-19 illustrate examples of cross-sectional views of intermediatestages in the sequential fabrication of a Fin FET device 300 inaccordance with some embodiments of the present disclosure. Not all ofthe depicted components may be required, however, and one or moreimplementations may include additional components not shown in thefigure. Variations in the arrangement and type of the components may bemade without departing from the scope of the claims as set forth herein.Additional processes, operations, material, components, differentcomponents, or fewer components may be provided. Further, the order ofthe operations may be changed.

FIG. 3 is a cross-sectional view of the Fin FET device 300 having asubstrate 110 at one of various stages of the sequential fabricationprocess according to an embodiment of the present disclosure. In thisembodiment, the substrate 110 includes a crystalline silicon substrate(e.g., wafer). A p-type substrate or n-type substrate may be used andthe substrate 110 may include various doped regions, depending on designrequirements. In some embodiments, the doped regions may be doped withp-type or n-type dopants. For example, the doped regions may be dopedwith p-type dopants, such as boron or BF₂; n-type dopants, such asphosphorus or arsenic; and/or combinations thereof. The doped regionsmay be configured for an n-type Fin FET, or alternatively configured fora p-type Fin FET.

In some alternative embodiments, the substrate 110 is made of some othersuitable elemental semiconductor, such as diamond or germanium; asuitable compound semiconductor, such as gallium arsenide, siliconcarbide, indium arsenide, or indium phosphide; or a suitable alloysemiconductor, such as silicon germanium carbide, gallium arsenicphosphide, or gallium indium phosphide. Also alternatively, thesubstrate may include an epitaxial layer. For example, the substrate mayhave an epitaxial layer overlying a bulk semiconductor. Further, thesubstrate may be strained for performance enhancement. For example, theepitaxial layer may include a semiconductor material different from thatof the bulk semiconductor, such as a layer of silicon germaniumoverlying bulk silicon or a layer of silicon overlying bulk silicongermanium. Such strained substrates may be formed by selective epitaxialgrowth (SEG). Furthermore, the substrate may include a SOI structure.Also alternatively, the substrate may include a buried dielectric layer,such as a buried oxide (BOX) layer, such as that formed by separation byimplantation of oxygen (SIMOX) technology, wafer bonding, SEG, or otherappropriate operation.

In one embodiment, a pad layer 304 a and a mask layer 304 b are formedon the semiconductor substrate 110. The pad layer 304 a may be a thinfilm having silicon oxide formed, for example, using a thermal oxidationoperation. The pad layer 304 a may act as an adhesion layer between thesemiconductor substrate 110 and the mask layer 304 b. The pad layer 304a may also act as an etch stop layer for etching the mask layer 304 b.In at least one embodiment, the mask layer 304 b is formed of siliconnitride, for example, using low-pressure chemical vapor deposition(LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The masklayer 304 b is used as a hard mask during subsequent patterningoperations. A photoresist layer 306 is formed on the mask layer 304 band is then patterned by a photolithography patterning operation,forming openings in the photoresist layer 306. The photoresist layer maybe removed after patterning of the mask layer 304 b and pad layer 304 aand before the trench etching.

The photolithography patterning operation may include photoresistcoating (e.g., spin-on coating), soft baking, mask aligning, exposing,post-exposure baking, developing a photoresist, rinsing, drying (e.g.,hard baking), other suitable operations, or combinations thereof.Alternatively, the photolithography patterning operation is implementedor replaced by other proper methods such as maskless photolithography,electron-beam writing, direct-writing, and/or ion-beam writing. Thephotolithography patterning operation yields the photoresist layer thatis used as a mask during a trench etching operation.

FIG. 4 is a cross-sectional view of the Fin FET device 300 at one ofvarious stages of the sequential fabrication process according to anembodiment of the present disclosure. The mask layer 304 b and pad layer304 a are etched to expose underlying semiconductor substrate 110. Theexposed semiconductor substrate 110 is then trench-etched to formtrenches 310 by using the patterned mask layer 304 b and pad layer 304 aas a mask.

In the trench etching operation, the substrate 110 may be etched byvarious methods, including a dry etch, a wet etch, or a combination ofdry etch and wet etch. The dry etching operation may implementfluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₄F₈),chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃),bromine-containing gas (e.g., HBr and/or CHBr₃), oxygen-containing gas,iodine-containing gas, other suitable gases and/or plasmas, orcombinations thereof.

Next, a wet cleaning operation may be performed to remove a native oxideof the semiconductor substrate 110. The cleaning may be performed usingdilute hydrofluoric (DHF) acid. Portions of the semiconductor substrate110 between trenches 310 form semiconductor fins 120. The fins 120 maybe arranged in columns (viewed from on top of the Fin FET device 300)parallel to each other, and closely spaced with respect to each other.Each of the fins 120 has a width W and a depth D, and are spaced apartfrom an adjacent fin by a width S of the trench 310. For example, thewidth W of the semiconductor fin 120 may be in a range from about 3 nmto about 30 nm in some embodiments.

FIG. 5 is a cross-sectional view of the Fin FET device 300 at one ofvarious stages of the sequential fabrication process according to anembodiment of the present disclosure. Trenches 310 are filled with oneor more layers of a dielectric material 314. The dielectric material 314may include silicon oxide. In one or more implementations, thedielectric material 314 is made of, for example, silicon dioxide formedby LPCVD (low pressure chemical vapor deposition), plasma-CVD orflowable CVD. In the flowable CVD, flowable dielectric materials insteadof silicon oxide are deposited. Flowable dielectric materials, as theirname suggests, can “flow” during deposition to fill gaps or spaces witha high aspect ratio. Usually, various chemistries are added tosilicon-containing precursors to allow the deposited film to flow. Insome embodiments, nitrogen hydride bonds are added. Examples of flowabledielectric precursors, particularly flowable silicon oxide precursors,include a silicate, a siloxane, a methyl silsesquioxane (MSQ), ahydrogen silsesquioxane (HSQ), an MSQ/HSQ a perhydrosilazane (TCPS), aperhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or asilyl-amine, such as trisilylamine (TSA). These flowable silicon oxidematerials are formed in a multiple-operation process. After the flowablefilm is deposited, it is cured and then annealed to remove un-desiredelement(s) to form silicon oxide. When the un-desired element(s) isremoved, the flowable film densifies and shrinks. In some embodiments,multiple anneal operations are conducted. The flowable film is thencured and annealed.

In some embodiments, other dielectric materials, such as siliconnitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or alow-K dielectric material, may also be used to form the dielectricmaterial 314. In an embodiment, the dielectric material 314 is formedusing a high-density-plasma (HDP) CVD operation, using silane (SiH₄) andoxygen (O₂) as reacting precursors. In other embodiments, the dielectricmaterial 314 may be formed using a sub-atmospheric CVD (SACVD) operationor high aspect-ratio process (HARP), in which process gases may includetetraethylorthosilicate (TEOS) and/or ozone (O₃). In yet otherembodiments, the dielectric material 314 may be formed using aspin-on-dielectric (SOD) operation, such as hydrogen silsesquioxane(HSQ) or methyl silsesquioxane (MSQ). In some embodiments, the filledrecess region (or the trenches 310) may have a multi-layer structuresuch as a thermal oxide liner layer filled with silicon nitride orsilicon oxide.

FIG. 6 is a cross-sectional view of the Fin FET device 300 at one ofvarious stages of the sequential fabrication process according to anembodiment of the present disclosure. After the deposition of thedielectric material 314, a chemical mechanical polish (CMP) and/or anetch-back operation are then performed, followed by the removal of themask layer 304 b and pad layer 304 a. An annealing operation may beperformed after the trenches 310 are filled with the dielectric material314. The annealing operation includes rapid thermal annealing (RTA),laser annealing operations, or other suitable annealing operations.

In at least one embodiment, the mask layer 304 b is formed of siliconnitride such that the mask layer 304 b is removed using a wet etchingoperation using H₃PO₄. The pad layer 304 a may be removed using diluteHF acid, if the pad layer 304 a is formed of silicon oxide. Theremaining portions of the dielectric material 314 in the trenches 310are hereinafter referred to as isolation regions 150. In someembodiments, the removal of the mask layer 304 b and the pad layer 304 ais performed after the recessing of the isolation regions 150, whichrecessing operation is shown in FIG. 7 .

FIG. 7 is a cross-sectional view of the Fin FET device 300 at one ofvarious stages of the sequential fabrication process according to anembodiment of the present disclosure. An etching operation may beperformed to etch isolation regions 150 to expose upper portions 322 ofthe semiconductor fins 120 from the isolation regions 150. The etchingoperation may include a dry etching operation, wet etching operation, orcombination dry and wet etching operations to remove portions of theisolation regions 150. It is understood that the etching operation maybe performed as one etching operation or multiple etching operations.

The remaining isolation regions 150 include top surfaces 317. Further,the upper portions 322 of the semiconductor fins 120 protruding over thetop surfaces 317 of the remaining isolation regions 150 thus are used toform an active area, such as a channel region, of the Fin FET device300. The upper portions 322 of the semiconductor fins 120 may includetop surfaces 323 and sidewalls 324. Height H of the upper portions 322of the semiconductor fins 120 from the top surface 317 of the isolationregions 150 may be in a range from about 6 nm to about 300 nm. In someembodiments, the height H is greater than 300 nm or smaller than 6 nm.For simplicity, the upper portion 322 of the semiconductor fin 120between adjacent isolation regions 150 is hereinafter referred to as thechannel region to illustrate each upper portion of the semiconductor fin120, in which the top surfaces 317 of the isolation regions 150 arelower than the top surface 323 of the semiconductor fin 120.

FIG. 8 is a perspective view of the n-type Fin FET device 802 and thep-type Fin FET device 804 at one of various stages of the sequentialfabrication process according to an embodiment of the subjecttechnology. A gate stack 320 is formed over the top surface 323 andsidewalls 324 of the semiconductor fin 120, extending to the topsurfaces 317 of the first isolation region 150 a and the secondisolation region 150 b. The gate stack 320 includes a gate dielectriclayer 130 and a gate electrode layer 140 over the gate dielectric layer130.

The gate dielectric layer 130 is formed to cover the top surface 323 andsidewalls 324 of at least a portion of the channel region of thesemiconductor fins 120. In some embodiments, the gate dielectric layer130 includes one or more layers of silicon oxide, silicon nitride,silicon oxy-nitride, or high-k dielectrics. High-k dielectrics mayinclude metal oxides. Examples of metal oxides used for high-kdielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La,Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixturesthereof. The gate dielectric layer 130 may be formed using a suitableoperation such as atomic layer deposition (ALD), chemical vapordeposition (CVD), physical vapor deposition (PVD), thermal oxidation,UV-ozone oxidation, or combinations thereof. The gate dielectric layer130 may further include an interfacial layer (not shown) to reducedamage between the gate dielectric layer 130 and the fin 120. Theinterfacial layer may include silicon oxide.

The gate electrode layer 140 is then formed on the gate dielectric layer130. In at least one embodiment, the gate electrode layer 140 covers theupper portion 322 of more than one semiconductor fin 120, so that theresulting n-type Fin FET device 802 includes more than one finstructure. In some alternative embodiments, each of the upper portions322 of the semiconductor fins 120 may be used to form a separate n-typeFin FET device 802. The gate electrode layer 140 may include a singlelayer or a multilayer structure. The gate electrode layer 140 mayinclude poly-silicon. Further, the gate electrode layer 140 may be dopedpoly-silicon with the uniform or non-uniform doping. In some alternativeembodiments, the gate electrode layer 140 may include a metal such asAl, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductivematerials with a work function compatible with the substrate material,or combinations thereof. The gate electrode layer 140 may be formedusing a suitable operation such as ALD, CVD, PVD, plating, orcombinations thereof. In some embodiments, a hard mask layer 332, whichhas been used to pattern a poly silicon layer, is formed on the gatestack 320.

In FIGS. 9-19 , a semiconductor device having one or more p-type Fin FETstructures (e.g., p-type Fin FET device 904) and one or more n-type FinFET structures (e.g., n-type Fin FET device 902) is illustrated. In thepresent disclosure, the Fin FET device 300 is depicted as one of then-type Fin FET structures but can be configured as another type of FinFET structure depending on implementation. For purposes ofsimplification, the subject matter in FIGS. 9-19 will be discussed inreference to the n-type Fin FET device 902 with additional referencemade to the p-type Fin FET device 904 for certain features of thesequential fabrication.

FIG. 9 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the subjecttechnology. In FIG. 9 , one gate structure is provided for two finstructures. In FIG. 9 , the n-type Fin FET device 902 is covered bysidewall spacer material 328 made of a dielectric layer along thevertical side of the gate stack 320. In some embodiments, the dielectriclayer includes one or more layers of silicon oxide, silicon nitride,silicon oxy-nitride, or other suitable material. The dielectric layermay include a single layer or multilayer structure. A blanket layer ofthe dielectric layer may be formed by CVD, PVD, ALD, or other suitabletechnique. Then, an anisotropic etching and/or etch-back operation isperformed on the dielectric layer to form a pair of sidewall spacermaterial 328 on two sides of the gate stack 320. During the formation ofthe gate stack 320, various cleaning/etching operations, which etch theSTI regions 150 and 150 b, are performed.

FIG. 10 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the subjecttechnology. The portion of the semiconductor fin 120 not covered by thegate stack 320 (FIG. 8 ) and sidewall spacer material 328 (FIG. 9 )formed thereover are recessed to form a recessed portion 326 of thesemiconductor fin 120 having a top surface 319 below the top surfaces317 of the first and second isolation regions 150 a, 150 b. In oneembodiment, using the sidewall spacer material 328 as hard masks, abiased etching operation is performed to recess top surface 319 of theupper portion 322 that are unprotected or exposed to form the recessedportion 326 of the semiconductor fin 120. In an embodiment, the etchingoperation may be performed using HBr and/or Cl₂ as etch gases.

FIG. 11 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. The structures depicted in FIG. 11 are produced byselectively growing a strained material (e.g., strained material 330 a,330 b) over the recessed portion 326 of the semiconductor fin 120 andextending over the top surfaces 317 of the first and second isolationregions 150 a, 150 b. Since the lattice constant of the strainedmaterial 330 a, 330 b is different from the channel region of thesemiconductor fin 120, the channel region of the semiconductor fin 120is strained or stressed to enable carrier mobility of the device andenhance the device performance. Although the strained material 330 a,330 b is formed separately with respect to each fin in FIG. 11 , thestrained material 330 a, 330 b may be connected to form a common strainmaterial structure.

In at least one embodiment, strained material 330 a, such as siliconcarbon (SiC) and/or silicon phosphide (SiP), is epitaxially grown by aLPCVD operation to form the source and drain regions of the n-type FinFET device 902. In at least another embodiment, strained material 330 b,such as silicon germanium (SiGe), is epitaxially grown by a LPCVDoperation to form the source and drain regions of the p-type Fin FETdevice 904.

The p-type Fin FET device 904 and the n-type Fin FET device 902 areseparately formed. In this regard, an n-type epitaxial region or p-typeepitaxial region can be defined using photolithography and etchingoperations. In FIGS. 10 and 11 , the n-type Fin FET 902 is covered by,for example, a silicon nitride (SiN) layer such that the n-type Fin FET902 is protected during the recess and source/drain formation in thep-type Fin FET 904. After the strained material 330 b is formed for thep-type Fin FET 904, the p-type Fin FET is covered by a SiN layer, andthen similar operations including recess formation and strain materialformation are performed on the n-type Fin FET 902.

FIG. 12A is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. FIG. 12B illustrates a cross-sectional view of the n-typeFin FET device 902 along B-B′ according to an embodiment of the presentdisclosure. FIG. 12C illustrates a plot of an example of dopingconcentrations over a range of depths according to an embodiment of thepresent disclosure.

While the p-type Fin FET device 904 is covered by a photoresist layer1202, a phosphorus dimer ion implantation 1204 is performed as shown inFIG. 12A. As discussed above, the present disclosure provides for thereduction of contact capacitance and increase in channel mobility forthe n-type Fin FET device 902 by providing relatively heavy and shallowdoping on a top surface of a phosphorus doped epitaxial layer (e.g., then-type epitaxial region of the n-type Fin FET device 902). Inparticular, the phosphorus dimer (P₂ ⁺) ion implantation 1204 isutilized to effectively introduce a higher chemical phosphorusconcentration and to increase a higher amorphous level than theconventional phosphorus ion implantation using P⁺.

The implantation of phosphorus dimer ions is performed on the topsurface of the strained material 330 a to provide a high phosphorusconcentration to reduce contact resistance with a contact from an upperlayer and to increase the tensile strain along the channel regionthereby increasing the effective electron mobility of the n-typechannel. In this regard, the higher tensile strain can cause a decreasein the bulk lattice parameter in the channel region, such as from about0.543 nm to about 0.537 nm based on a 10% to 15% increase in phosphorusconcentration at the top surface of the strain material 330 a.

In some aspects, the phosphorus dimer ion implantation 1204 implants thedopant species using implant energy in a range from about 0.1 KeV toabout 500 KeV. In some embodiments, the implant dosage is in a rangefrom about 1×10¹⁵ atoms/cm³ to about 4×10¹⁵ atoms/cm³. In otherembodiments, the acceleration voltage is in a range from about 10 KeV toabout 100 KeV. In certain embodiments, the acceleration voltage is in arange from about 1 KeV to about 10 KeV. The tilt angle of the ion beamrelative to a vertical axis 1206 may vary in a range from about 0degrees to about 45 degrees. In addition, the ions can be implanted fromtwo directions (e.g., 0 degrees and 180 degrees by rotating the wafer)or four directions.

In some embodiments, the phosphorus dimer ion implantation 1204 of thefirst doping agent includes cooling at least the first fin structure andthe first strain material to a temperature below about −20° C.; hence, acryo-implantation. The temperature in the cryo-implantation can be in arange from about −10° C. to about −100° C. For example, the n-type FinFET device 902 including the n-type epitaxial region (or n-type strainmaterial) can be cooled from a room temperature to a temperature of −20°C. in some embodiments, or below −20° C. in other embodiments.

The phosphorus dimer ion implantation 1204 at these cold temperaturesinduces more activated phosphorus dopants on the surface due to therelatively high amorphous degree (or lower activation energy needed foractivation). As a result, the phosphorus dimer ion implantation 1204performed as a cryo-implantation can cause more lateral straggle tooccur compared to room-temperature implantation. This is because thecolder temperatures cause the implanted phosphorus atoms to move furtherlaterally relative to the point of initial penetration of the topsurface of the strain material 330 a. As used herein, the term “lateralvariance” refers to the lateral movement of ions along an axis aboutorthogonal to the surface of initial penetration.

In one or more implementations, implanted ions (impurities) in the firstregion 1210 have a first lateral variance and impurities in the secondregion 1212 have a second lateral variance where the first lateralvariance is greater than the second lateral variance due to thephosphorus dimer ion implantation 1204 performed as thecryo-implantation operation. As such, the increase in lateral variancecauses a reduction in contact resistance of due to the relatively shortchannel length of the n-type Fin FET device 902. Following thephosphorus dimer ion implantation, the photoresist layer 1202, forexample, may be removed. In addition, a thermal anneal operation is thenperformed (see FIG. 13 ). In some embodiments, cluster ions ofphosphorus are used instead of phosphorus dimer ions.

As shown below in Table 1, two different examples of phosphorus dimerimplantation and anneal are described. For example, devices A isimplanted with phosphorus dimer dopants at room temperature; whereasdevice B is implanted with phosphorus dimer dopants at cryo temperatures(e.g., at about −20° C.). Both devices are implanted with the samedosage (between about 1×10¹⁵ atoms/cm³ and about 4×10¹⁵ atoms/cm³) andsame anneal temperature (between about 950 and about 1250° C.). Comparedto device A, device B exhibits a lower total resistance (0.98 relativeto the resistance value of device A) and about 3% higher ingate-to-drain capacitance performance, and about 2% higher ingate-to-gate capacitance performance. The implantation at cryotemperatures yields a higher performing device with respect to totalresistance and capacitance performance to provide for the increase inchannel mobility for the NMOS Fin FET structure.

TABLE 1 S/D Phosphorus Dimer Implantation and Thermal Optimization A BN + S/D Implantation Temperature Room Temp −20° C. Relative TotalResistance 1 0.98 Relative Parasitic Resistance 1 0.99 Relative ChannelResistance 1 0.99 Relative Gate-Drain Capacitance 1 1.03 RelativeGate-to-Gate Capacitance 1 1.02

As shown in FIG. 12B, the n-type epitaxial region may have a firstregion 1210 (including the top surface) having a first thickness (T₁) ina range from about 0.1 nanometers (nm) to about 8 nm. The first region1210 may receive the higher concentration of phosphorus due to thephosphorus dimer ion implantation 1204 compared to a second region 1212disposed below the first region 1210. In some embodiments, the secondregion 1212 has a second thickness (T₂) in a range from about 25 nm toabout 60 nm, and contains a doping concentration based on theepitaxially grown silicon phosphide during the epitaxial growthoperation or a single atom phosphorus implantation that may beoptionally performed.

FIG. 12C illustrates a plot of an example of a SIMS (Secondary Ion MassSpectroscopy) profile of doping concentrations over a range of depths.As shown in FIG. 12C, the peak phosphorus dimer doping density (labeledas “SiP+P2 I/I+μSSA”) in the present embodiment is greater than about1×10²² atoms/cm³ (e.g., region 1252), and is located at less than a fewnm from the top surface of the implanted silicon region (e.g., the firstregion 1210 of FIG. 12B) such that the doping concentration is increasednear the surface. In contrast, the peak single-atom phosphorus dopingdensity (labeled as “SiP dep”) and the peak single-atom phosphorusdoping density with micro-sub second anneal (labeled as “SiP+μSSA”) aremagnitudes smaller than the peak phosphorus dimer doping density. FIG.12C shows that by using P₂ ⁺ ion implantation, a higher amount ofimpurities can be introduced at a portion closer to the surface of thesource/drain epitaxial regions.

FIG. 13 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. After the phosphorus dimer ion implantation 1204, a thermalanneal operation 1302 with temperatures in a range from about 950° C. toabout 1250° C. may be performed to activate the implanted phosphorus. Asdiscussed above, the increase in phosphorus concentration (via thephosphorus dimer ion implantation) increases the tensile strain appliedon the channel region of the n-type Fin FET device 902. In this regard,the increase in tensile strain enhances channel electron mobility.

The application of the thermal anneal operation 1302 may include heatingthe semiconductor device, particularly the n-type Fin FET device 902, toa temperature in a range from 900° C. to 1000° C. in some embodiments,or to a temperature in a range from about 1000° C. to about 1300° C. inother embodiments. In some embodiments, the thermal anneal operation1302 is applied for a duration in a range from about 1 second to about10 seconds. In some aspects, the thermal anneal operation 1302 isapplied uniformly across the n-type Fin FET device 902 and the p-typeFin FET device 904. The thermal anneal operation 1302 may include ananneal operation selected from a group including RTA, flash anneal,sub-second anneal (SSA), micro-sub second anneal (μSSA), laser anneal,etc. In some embodiments, RTA is performed at a temperature in a rangefrom about 950° C. to about 1250° C. for about 7 to about 10 seconds, insome embodiments. Alternatively, the anneal operations are performed ata temperature in a range from about 1050 to about 1150° C. for about 1to about 6 seconds, in other embodiments. In other embodiments, μSSA isperformed at a temperature in a range from about 950 to about 1150° C.for about 10 to about 500 micro seconds.

FIG. 14 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. After forming the source/drain regions (e.g., the strainmaterial 330 a, the strain material 330 b), an operation of depositing acontact etch stop layer 1402 (CESL) is performed. In this example, theCESL 1402 may be applied as a layer uniformly over the n-type Fin FETdevice 902 and the p-type Fin FET device 904.

FIG. 15 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of fabricationaccording to an embodiment of the present disclosure. The CESL operation(see, FIG. 14 ) is followed by an operation of depositing an interlayerdielectric (ILD) layer 1502. The ILD layer 1502 is deposited by asuitable technique, such as CVD. In this embodiment, the ILD layer 1502is applied as a layer uniformly over the n-type Fin FET device 902 andthe p-type Fin FET device 904. The ILD layer 1502 includes a dielectricmaterial, such as one or more layers of silicon oxide, silicon nitride,a low-k dielectric material or a combination thereof.

FIG. 16 is a perspective view of the n-type Fin FET device 902 and thep-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. The ILD layer 1502 and the hard mask are subsequentlyplanarized by a CMP operation, resulting in the structure shown in FIG.16 .

In embodiments of the disclosure, the source/drain electrodes (contacts)is formed by patterning the ILD layer 1502, such as a photolithographicoperation to form openings exposing the strain material 330 a and 330 b.A suitable conductive material, such as copper, tungsten, nickel,titanium, or the like, is deposited in the openings. In someembodiments, a metal silicide is formed at the conductive material andsource/drain interface to improve conductivity at the interface. In oneexample, a damascene and/or dual damascene operation is used to formcopper-based multilayer interconnection structures. In anotherembodiment, tungsten is used to form tungsten plugs in the openings.

In this embodiment, an STI first/gate last method is implemented. Manyof the operations in this embodiment are the same or similar to theoperations of a STI first/gate first method. The methods are the samethrough the operation of removing a portion of the STI regions.

In order to use a high-k metal gate (HK/MG), an operation of depositinga dummy gate dielectric overlying the exposed end portions of the fins,an operation of depositing a dummy gate, and an operation of patterningthe dummy gate are performed. After patterning the dummy gate, the nextoperations are the same or similar to the STI first/gate first methoduntil after the operation of CMP of the ILD layer 1502.

FIG. 17 is a cross-sectional view of the n-type Fin FET device 902 andthe p-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. After CMP of the ILD layer 1502, an operation of removingthe dummy gate and an operation of removing the dummy gate dielectricare also performed. The dummy gate and dummy gate dielectric are removedusing suitable etching operations.

FIG. 18 is a cross-sectional view of the n-type Fin FET device 902 andthe p-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. Subsequently, an operation of depositing a high k metal gate1802 (HK/MG) on a high k gate dielectric 1804 occurs. According toembodiments of the disclosure, the high k gate dielectric 1804 mayinclude one or more layers of HfO₂, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO,zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃)alloy, other suitable high-k dielectric materials, or combinationsthereof. The high k metal gate 1802 material may include one or morelayers of Ti, TiN, titanium-aluminum alloy, Al, AlN, Ta, TaN, TaC, TaCN,TaSi, and the like.

FIG. 19 is a cross-sectional view of the n-type Fin FET device 902 andthe p-type Fin FET device 904 at one of various stages of the sequentialfabrication process according to an embodiment of the presentdisclosure. After formation of the HK/MG electrode structure, thesource/drain electrodes are patterned in a similar manner to the STIfirst/gate first method.

In other embodiments, a method for fabricating the Fin FET device 300utilizes an EPI first/gate first method or EPI first/gate last method.In the EPI first methods, an epitaxial layer is formed on the substrate110, and then the epitaxial layer is subsequently patterned to form fins(e.g., the semiconductor fins 120). Many of the operations in the EPIfirst embodiments are the same or similar to the operations of the STIfirst methods.

Subsequent processing according to embodiments of the present disclosuremay also form various contacts/vias/lines and multilayer interconnectfeatures (e.g., metal layers and interlayer dielectrics) on thesemiconductor substrate 110, configured to connect the various featuresor structures of the Fin FET device 300. For example, a multilayerinterconnection includes vertical interconnects, such as conventionalvias or contacts, and horizontal interconnects, such as metal lines.

The Fin FET device 300 serves only as one example. The Fin FET device300 may be used in various applications such as digital circuit, imagingsensor devices, a hetero-semiconductor device, dynamic random accessmemory (DRAM) cell, a single electron transistor (SET), and/or othermicroelectronic devices (collectively referred to herein asmicroelectronic devices). Of course, aspects of the present disclosureare also applicable and/or readily adaptable to other type oftransistor, including single-gate transistors, double-gate transistors,and other multiple-gate transistors, and may be employed in manydifferent applications, including sensor cells, memory cells, logiccells, and others.

The present disclosure provides for the reduction of contact capacitanceand increase in channel mobility for NMOS Fin FET structures byproviding relatively heavy and shallow doping on a top surface of thephosphorus doped silicon-containing epitaxial layering. In particular, aphosphorus dimer (P₂ ⁺) ion implantation is utilized after the epitaxiallayering operation in order to effectively incorporate a higher chemicalphosphorus concentration and amorphous level than the conventionalphosphorus ion implantation under a same implantation dosage. Thephosphorus dimer ion implantation may be, or may be a part of, acryo-implantation with temperatures below −20° C. to induce a higheramorphous level (or lower activation energy).

In an embodiment, a method of fabricating a Fin FET device includesproviding a substrate having a first fin structure and a second finstructure. The method includes forming an isolation layer on thesubstrate, in which the isolation layer is formed adjacent to the firstfin structure and the second fin structure. The method includes forminga first gate structure on at least a portion of the first fin structureand the isolation layer. The method includes forming a second gatestructure on at least a portion of the second fin structure and theisolation layer. The method includes forming a first strain material byan epitaxial growth operation, in which the first strain materialprovides stress to a channel region of the first fin structure. Themethod includes forming a second strain material by the epitaxial growthoperation, in which the second strain material provides stress to achannel region of the second fin structure. The method also includesimplanting a first doping agent to at least a first region of the firststrain material, in which the first region has a first dopingconcentration of the first doping agent. In this embodiment, the firstdoping concentration is greater than a second doping concentration of asecond doping agent in a second region of the first strain material. Themethod also includes applying a thermal anneal operation to at least thefirst fin structure and the first strain material, in which the channelregion of the first fin structure has greater channel mobility than thechannel region of the second fin structure, by at least the thermalanneal operation.

In another embodiment, a method of fabricating a Fin FET device includesproviding a substrate having a fin structure. The method includesforming an isolation layer on the substrate, in which the isolationlayer is formed adjacent to the fin structure. The method includesforming a gate structure on at least a portion of the fin structure andthe isolation layer. The method includes forming a strain material by anepitaxial growth operation, in which the strain material provides stressto a channel region of the fin structure. The method includes implantinga first doping agent to at least a first region of the strain material,in which the first region has a first doping concentration of the firstdoping agent, and the first doping concentration being greater than asecond doping concentration of a second doping agent in a second regionof the strain material. The method also includes applying a thermalanneal operation to at least the fin structure and the strain material,in which the channel region of the fin structure has greater channelmobility than the channel region of a second fin structure on thesubstrate, by at least the thermal anneal operation.

In still another embodiment, a semiconductor device includes asubstrate, a first fin structure and a second fin structure. Thesemiconductor device includes an isolation layer formed on thesubstrate, in which the isolation layer is formed adjacent to the firstfin structure and the second fin structure. The semiconductor deviceincludes a first gate structure formed on at least a portion of thefirst fin structure and the isolation layer. The semiconductor deviceincludes a second gate structure formed on at least a portion of thesecond fin structure and the isolation layer. The semiconductor deviceincludes a first epitaxial layer including a first strained materialthat provides stress to a channel region of the first fin structure. Thesemiconductor device includes a second epitaxial layer including asecond strained material that provides stress to a channel region of thesecond fin structure, in which the second epitaxial layer has a firstregion and a second region. The first region has a first dopingconcentration of a first doping agent and the second region has a seconddoping concentration of a second doping agent. In this embodiment, thefirst doping concentration is greater than the second dopingconcentration.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother operations and structures for carrying out the same purposesand/or achieving the same advantages of the embodiments introducedherein. Those skilled in the art should also realize that suchequivalent constructions do not depart from the spirit and scope of thepresent disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A semiconductor device, comprising: one or moren-type Fin FET structures; and one or more p-type Fin FET structures,wherein the n-type Fin FET structure comprises: a first gate structureformed over a channel region of a first fin structure; and firstsource/drain regions formed on the first fin structure on opposing sidesof the first gate structure; and wherein the first source/drain regionshave a first region and a second region, the first region being locatedcloser to a surface of the first source/drain regions, the first regionhas a first dopant and the second region has a second dopant, and thefirst region has a first doping concentration of a first dopant ofgreater than 1×10²² atoms/cm³.
 2. The semiconductor device of claim 1,wherein the first dopant is a phosphorous dimer dopant and the seconddopant is a phosphorous dopant.
 3. The semiconductor device of claim 1,wherein the first source/drain regions comprise SiGe.
 4. Thesemiconductor device of claim 1, wherein the p-type Fin FET structureincludes second source/drain regions, and the second source/drainregions comprise SiP or SiC.
 5. The semiconductor device of claim 1,wherein the p-type Fin FET structures include a first fin structurehaving a channel region and a second fin structure having a channelregion, and the channel region of the first fin structure has a higherchannel mobility than the channel region of the second fin structure. 6.The semiconductor device of claim 1, wherein a doping concentration ofthe second dopant is in a range from 1×10¹⁵ atoms/cm³ to 4×10¹⁵atoms/cm³.
 7. The semiconductor device of claim 1, wherein the firstdopant is disposed over a top surface of the second region.
 8. Asemiconductor device, comprising: one or more p-type Fin FET structures,wherein the p-type Fin FET structure comprises a first gate structureformed over a channel region of a first fin structure; one or moren-type Fin FET structures, wherein the n-type Fin FET structurecomprises: a second gate structure formed over a channel region of asecond fin structure; and first source/drain regions formed on thesecond fin structure on opposing sides of the second gate structure; andwherein the first source/drain regions have a first region and a secondregion, the first region being located closer to a surface of the firstsource/drain regions, the first region has a first dopant and the secondregion has a second dopant, and wherein the channel region of the secondfin structure has a higher channel mobility than the channel region ofthe first fin structure.
 9. The semiconductor device of claim 8, whereinthe first dopant is a phosphorous dimer dopant and the second dopant isa phosphorous dopant.
 10. The semiconductor device of claim 8, whereinthe first source/drain regions comprise SiGe.
 11. The semiconductordevice of claim 8, wherein the p-type Fin FET structures include secondsource/drain regions, and the second source/drain structures compriseSiP or SiC.
 12. The semiconductor device of claim 8, wherein the p-typeFin FET structures include a first fin structure having a channel regionand a second fin structure having a channel region, and the channelregion of the first fin structure has a higher channel mobility than thechannel region of the second fin structure.
 13. The semiconductor deviceof claim 8, wherein a doping concentration of the second dopant is in arange from 1×10¹⁵ atoms/cm³ to 4×10¹⁵ atoms/cm³.
 14. The semiconductordevice of claim 8, wherein the first dopant is disposed over a topsurface of the second region.
 15. A semiconductor device, comprising:one or more n-type Fin FET structures; and one or more p-type Fin FETstructures, wherein the n-type Fin FET structure comprises: a first gatestructure formed over a channel region of a first fin structure; andfirst source/drain regions formed on the first fin structure on opposingsides of the first gate structure; and wherein the first source/drainregions have a first region and a second region, the first region beinglocated closer to a surface of the first source/drain regions, the firstregion has a first dopant and the second region has a second dopant, andthe first region has a first doping concentration of the first dopantand the second region has a second doping concentration of the seconddopant, the first doping concentration is greater than the second dopingconcentration, and a thickness of the first region from a surface of thefirst source/drain regions to the second region ranges from 0.1 nm to 8nm.
 16. The semiconductor device of claim 15, wherein the first dopantis a phosphorous dimer dopant and the second dopant is a phosphorousdopant.
 17. The semiconductor device of claim 15, wherein the firstsource/drain regions comprise SiGe.
 18. The semiconductor device ofclaim 15, wherein the p-type Fin FET structures include secondsource/drain regions, and the second source/drain structures compriseSiP or SiC.
 19. The semiconductor device of claim 15, wherein the p-typeFin FET structures include a first fin structure having a channel regionand a second fin structure having a channel region, and the channelregion of the first fin structure has a higher channel mobility than thechannel region of the second fin structure.
 20. The semiconductor deviceof claim 15, wherein the first doping concentration of the first dopantis greater than 1×10²² atoms/cm³